Aspects of the invention relate generally to integrated circuits. More particularly, various aspects of the invention relate to metrology in integrated circuits.
Developing and testing integrated circuit (IC) devices, also referred to as semiconductor devices, involves designing, manufacturing and testing these devices according to desired operating parameters. Quality assurance has been a concern in the development, fabrication and testing of IC devices, but is particularly important as these devices become ever more complex.
Optical proximity correct (OPC) is known in the art as a photolithography enhancement mechanism used to compensate for errors in forming images due to diffraction and/or process effects. OPC helps to compensate for the inability of light to maintain edge placement integrity when used to form shapes, e.g., IC lines, vias, connections, switches, etc. OPC corrects for errors by adding polygons, moving edges, or otherwise modifying a photomask to compensate for the deviation caused by the light used in the subsequent lithography steps. OPC is conventionally performed in a feedback-based process, where a target shape is used to design a mask, which is then modified according to an OPC algorithm, and then a final contour is formed based upon the mask produced by the OPC algorithm. In some cases, the final contour can be produced (either physically or in simulation) in order to test the OPC algorithm and/or drive changes to that algorithm.
The OPC algorithms are conventionally based upon process variation bands, which is a statistical indicator of the likelihood of one or more portions of the IC fabrication process forming an element that deviates from the target. Process variation band based calculations conventionally focus on physical parameters such as minimum widths of lines, vias, devices (transistors, etc.) as well as minimum spacings between the lines, vias and/or devices in order to design the OPC algorithm. These conventional process variation band based calculations assume that these physical parameters are uniform across all elements (e.g., lines, vias, devices, etc.) in an IC layout. However, these conventional process variation band based calculations can be less reliable as devices begin to shrink in scale, particularly when focused on electrical parameters. Interactions with electrical parameters can lead to voltage and current-dependent failures such as time-dependent dielectric breakdown (TDDB) and electromigration.